Semiconductor memory apparatus and training method using the same

ABSTRACT

A semiconductor memory apparatus may include a cyclic redundancy check (CRC) circuit block electrically coupled with a first pad, and configured to generate internal CRC information from data received from the first pad. The semiconductor memory apparatus may also include a comparison unit configured to compare external CRC information received from outside the semiconductor memory apparatus with the internal CRC information, and generate a read training result signal.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) toKorean application number 10-2014-0071248, filed on Jun. 12, 2014, inthe Korean Intellectual Property Office, which is incorporated herein byreference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to semiconductor integratedcircuits, and more particularly, to semiconductor memory apparatuses andtraining methods using the same.

2. Related Art

A semiconductor memory apparatus may be configured to store data andoutput the stored data. This type of semiconductor memory apparatus maybe applied to a system and may be controlled by a controller.

If the controller and the semiconductor memory apparatus areelectrically coupled with each other, the controller may perform atraining operation together with the semiconductor memory apparatus.After the training operation is performed, a normal operation may thenbe performed.

The training operation is an operation for controlling the marginbetween the controller and the semiconductor memory apparatus. Thenormal operation is an operation for the semiconductor memory apparatusto store data and output the stored data under the control of thecontroller.

SUMMARY

In an embodiment, a semiconductor memory apparatus may include a cyclicredundancy check (CRC) circuit block electrically coupled with a datapad, and configured to generate internal CRC information from datareceived from the data pad. The semiconductor memory apparatus may alsoinclude a comparison unit configured to compare external CRC informationreceived from outside the semiconductor memory apparatus with theinternal CRC information, and may generate a read training resultsignal.

In an embodiment, a semiconductor memory apparatus may include a CRCcircuit block configured to receive data from a first pad and generateinternal CRC information, a training determination block configured tocompare the internal CRC information with external CRC information andgenerate a read training result signal, and generate a combination pulsein response to the read training result signal and a first read pipelatch control pulse. The semiconductor memory apparatus may also includea write pipe latch block configured to receive and latch the data, andoutput latched data. The semiconductor memory apparatus may include afirst selection block configured to electrically couple an output nodeof the write pipe latch block with an input node of a read pipe latchblock in response to a training control signal, the read pipe latchblock configured to receive and latch data inputted through the inputnode thereof and output latched data to the first pad, in response to apipe input signal and a pipe output signal. The semiconductor memoryapparatus may also include a read pipe latch control block configured togenerate the pipe input signal and the pipe output signal in response toa second read pipe latch control pulse and the combination pulse.

In an embodiment, a training method of a semiconductor memory apparatusmay include a read training operation including an internal CRCinformation generating action of receiving data and generating internalCRC information, a comparing action of comparing the internal CRCinformation and external CRC information inputted from an exterior andgenerating a read training result signal, and a first outputting actionof outputting the read training result signal to an exterior. Thetraining method of a semiconductor memory apparatus may also include anaction of inputting the data used to generate the internal CRCinformation, to a read pipe latch block, and latching the inputted data,when the read training result signal is at a predetermined level. Thetraining method of a semiconductor memory apparatus may include a writetraining operation including a second outputting action of outputtingthe data latched by the read pipe latch block outside of thesemiconductor memory apparatus.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a configuration diagram illustrating a representation of anexample of a semiconductor memory apparatus in accordance with anembodiment.

FIG. 2 is a configuration diagram of a representation of the pulsegeneration unit illustrated in FIG. 1.

FIG. 3 is a configuration diagram of a representation of the signalcombination unit illustrated in FIG. 1.

FIG. 4 is a configuration diagram of a representation of the firstselection block illustrated in FIG. 1.

FIG. 5 illustrates a block diagram of an example of a representation ofa system employing the methods and semiconductor memory apparatuses inaccordance with the embodiments discussed above with relation to FIGS.1-4.

DETAILED DESCRIPTION

Hereinafter, a semiconductor memory apparatus will be described belowwith reference to the accompanying drawings through various examples ofembodiments.

Referring to FIG. 1, a semiconductor memory apparatus in accordance withan embodiment may include first to third pads PAD1, PAD2 and PAD3. Thesemiconductor memory apparatus may also include a cyclic redundancycheck (CRC) circuit block 100, a training determination block 200, and awrite pipe latch block 300. The semiconductor memory apparatus may alsoinclude a first selection block 400, a read pipe latch control block500, and a read pipe latch block 600. The semiconductor memory apparatusmay include a second selection block 700 and a third selection block800.

As indicated by the arrows illustrated in FIG. 1, the first pad PAD1 maybe inputted with or receive data Data from a source exterior to thesemiconductor memory apparatus. The first pad PAD1 may also output dataData exterior from the semiconductor memory apparatus. The first padPAD1 may be a data pad.

The second pad PAD2 may be inputted with or receive an address from asource exterior to the semiconductor memory apparatus in a normaloperation. In a training operation, the second pad PAD2 may be inputtedwith or receive external CRC information CRC_E. The second pad PAD2 maybe an address input pad.

The third pad PAD3 may output internal CRC information CRC_I exterior tothe semiconductor memory apparatus in the normal operation. In thetraining operation, the third pad PAD3 may output a read training resultsignal RDTR_r exterior to the semiconductor memory apparatus. The thirdpad PAD3 may be a CRC output pad.

The CRC circuit block 100 may be inputted with the data Data inputtedfrom the first pad PAD1 and may generate the internal

CRC information CRC_I. CRC stands for cyclic redundancy check. The CRCcircuit block 100 may be a CRC circuit which is generally known in theart.

The training determination block 200 may compare the internal CRCinformation CRC_I and the external CRC information CRC_E and maygenerate the read training result signal RDTR_r, and may generate acombination pulse C_p in response to the read training result signalRDTR_r and a first read pipe latch control pulse RDCTRL1_p. For example,the training determination block 200 may enable the read training resultsignal RDTR_r when the internal CRC information CRC_I and the externalCRC information CRC_E are the same with each other, and may generate thecombination pulse C_p when the read training result signal RDTR_r isenabled (i.e., at a predetermined level or voltage logic level) or thefirst read pipe latch control pulse RDCTRL1_p is inputted or received bythe training determination block 200.

As illustrated in FIG. 1, the training determination block 200 mayinclude a comparison unit 210, a pulse generation unit 220, and a signalcombination unit 230.

The comparison unit 210 may enable the read training result signalRDTR_r when the internal CRC information CRC_I and the external CRCinformation CRC_E are the same with each other. The comparison unit 210may disable the read training result signal RDTR_r when the internal CRCinformation CRC_I and the external CRC information CRC_E are differentfrom each other.

The pulse generation unit 220 may generate a result pulse P_r when theread training result signal RDTR_r is enabled.

Referring to FIG. 2, the pulse generation unit 220 may include a delaysection 221, first and second inverters IV1 and IV2, and a NAND gateND1. The delay section 221 may be inputted with the read training resultsignal RDTR_r. The first inverter IV1 may be inputted with the outputsignal of the delay section 221. The NAND gate ND1 may be inputted withthe read training result signal RDTR_r and the output signal of thefirst inverter IV1. The second inverter IV2 may be inputted with theoutput signal of the NAND gate ND1 and may generate the result pulseP_r. The pulse generation unit 220 configured in this way generates theresult pulse P_r which is enabled to a high level, when the readtraining result signal RDTR_r is enabled to a high level.

The signal combination unit 230 may output the combination pulse C_pwhen the result pulse P_r or the first read pipe latch control pulseRDCTRL1_p is inputted or received. The first read pipe latch controlpulse RDCTRL1_p, as a pulse which is internally generated in a readoperation of the semiconductor memory apparatus, may be a pulse forinputting and storing the data stored in the semiconductor memoryapparatus (for example, the data transmitted from a read data lineRD_Line), to and in the read pipe latch block 600, in the readoperation.

Referring to FIG. 3, the signal combination unit 230 may include a NORgate NOR1 and a third inverter IV3. The NOR gate NOR1 may be inputtedwith the result pulse P_r and the first read pipe latch control pulseRDCTRL1_p. The third inverter IV3 may be inputted with the output signalof the NOR gate NOR1 and may output the combination pulse C_p.

The write pipe latch block 300 may be inputted with and may latch thedata Data inputted from the first pad PAD1, and may output latched datato its output node Node_1.

The first selection block 400 may electrically couple the output nodeNode_1 of the write pipe latch block 300 to an input node Node_2 of theread pipe latch block 600 in response to a training control signal TR_s.For example, the first selection block 400 may electrically couple theoutput node Node_1 of the write pipe latch block 300 to the input nodeNode_2 of the read pipe latch block 600 when the training control signalTR_s is enabled. When the training control signal TR_s is disabled, thefirst selection block 400 may electrically couple the output node Node_1of the write pipe latch block 300 to a write data line WT_Line, and mayelectrically couple the input node Node_2 of the read pipe latch block600 to the read data line RD_Line. The training control signal TR_s, asa signal which is enabled when performing the training operation betweena controller and the semiconductor memory apparatus, is a signal whichis outputted from an exterior of the semiconductor memory apparatus,that is, the controller and received by the semiconductor memoryapparatus or for example, the first selection block 400.

Referring to FIG. 4, the first selection block 400 may include first tothird switches 410, 420, and 430.

The first switch 410 may electrically couple or decouple the output nodeNode_1 of the write pipe latch block 300 and the input node Node_2 ofthe read pipe latch block 600 in response to the training control signalTR_s. For example, the first switch 410 may electrically couple theoutput node Node_1 of the write pipe latch block 300 and the input nodeNode_2 of the read pipe latch block 600 when the training control signalTR_s is enabled. The first switch 410 may electrically decouple theoutput node Node_1 of the write pipe latch block 300 and the input nodeNode_2 of the read pipe latch block 600 when the training control signalTR_s is disabled.

The second switch 420 may electrically couple or decouple the outputnode Node_1 of the write pipe latch block 300 and the write data lineWT_Line in response to the training control signal TR_s. For example,the second switch 420 may electrically couple the output node Node_1 ofthe write pipe latch block 300 and the write data line WT_Line when thetraining control signal TR_s is disabled. The second switch 420 mayelectrically decouple the output node Node_1 of the write pipe latchblock 300 and the write data line WT_Line when the training controlsignal TR_s is enabled.

The third switch 430 may electrically couple or decouple the input nodeNode_2 of the read pipe latch block 600 and the read data line RD_Linein response to the training control signal TR_s. For example, the thirdswitch 430 may electrically couple the input node Node_2 of the readpipe latch block 600 and the read data line RD_Line when the trainingcontrol signal TR_s is disabled. The third switch 430 may electricallydecouple the input node Node_2 of the read pipe latch block 600 and theread data line RD_Line when the training control signal TR_s is enabled.

Referring to FIG. 1, the read pipe latch control block 500 may enable apipe input signal PIN when the combination pulse C_p is inputted orreceived by the read pipe latch control block 500. The read pipe latchcontrol block 500 may enable a pipe output signal POUT when a secondread pipe latch control pulse RDCTRL2_p is enabled. The second read pipelatch control pulse RDCTRL2_p, as a pulse which is internally generatedin the read operation of the semiconductor memory apparatus, may be apulse for outputting the data stored in the read pipe latch block 600 tothe first pad PAD1 in the read operation.

The read pipe latch control block 500 may include an input control unit510 and an output control unit 520. The input control unit 510 mayenable the pipe input signal PIN when the combination pulse C_p isinputted. The output control unit 520 may enable the pipe output signalPOUT when the second read pipe latch control pulse RDCTRL2_p isinputted.

The read pipe latch block 600 may be inputted with and may latch thedata inputted through the input node Node_2 of the read pipe latch block600 and may output latched data to the first pad PAD1, in response tothe pipe input signal PIN and the pipe output signal POUT. For example,the read pipe latch block 600 is inputted, through the input node Node_2thereof, with and latches data when the pipe input signal PIN isenabled. The read pipe latch block 600 may output the latched data tothe first pad PAD1 when the pipe output signal POUT is enabled.

The second selection block 700 may electrically couple the second padPAD2 and the comparison unit 210 of the training determination block 200and may transmit the external CRC information CRC_E to the comparisonunit 210 or may electrically couple the second pad PAD2 and an addressline ADD_Line, in response to the training control signal TR_s. Forexample, the second selection block 700 may transmit the signal inputtedthereto, to the comparison unit 210, when the training control signalTR_s is enabled, and may transmit the signal inputted thereto, to theaddress line ADD_Line, when the training control signal TR_s isdisabled. The second pad PAD2 may be inputted with the external CRCinformation CRC_E in the training operation, and may be inputted with anaddress (not illustrated) in the normal operation.

In response to the training control signal TR_s, the third selectionblock 800 may output the internal CRC information CRC_I or the readtraining result signal RDTR_r to the third pad PAD3. For example, thethird selection block 800 may output the read training result signalRDTR_r to the third pad PAD3 when the training control signal TR_s isenabled. The third selection block 800 may output the internal CRCinformation CRC_I to the third pad PAD3 when the training control signalTR_s is disabled.

A training method of the semiconductor memory apparatus in accordancewith an embodiment, configured as mentioned above, will be describedbelow.

Since the training operation is to be described, the training controlsignal TR_s may be assumed to be in an enabled state.

First, a read training operation will be described below.

The data Data is inputted to the CRC circuit block 100 and the writepipe latch block 300 through the first pad PAD1.

The CRC circuit block 100 is inputted with the data Data and generatesthe internal CRC information CRC_I.

The external CRC information CRC_E is inputted through the second padPAD2 and the second selection block 700.

The comparison unit 210 compares the internal CRC information CRC_I andthe external CRC information CRC_E and generates the read trainingresult signal RDTR_r. The comparison unit 210 enables the read trainingresult signal RDTR_r when the internal CRC information CRC_I and theexternal CRC information CRC_E are the same with each other.

The third selection block 300 outputs the read training result signalRDTR_r to the third pad PAD3.

If the read training result signal RDTR_r is enabled, the pulsegeneration unit 220 generates the result pulse P_r. If the pulsegeneration unit 220 generates the result pulse P_r, the combinationpulse C_p is generated, and the input control unit 510 enables the pipeinput signal PIN. If the pipe input signal PIN is enabled, the data Datainputted to the CRC circuit block 100, that is, the data Data latched bythe write pipe latch block 300 is inputted through the first selectionblock 400 to and is latched by the read pipe latch block 600.

In this way, as the read training result signal RDTR_r is outputted tothe third pad PAD3 and the data Data used to generate the internal CRCinformation CRC_I is stored in the read pipe latch block 600 when theread training result signal RDTR_r is enabled, the read trainingoperation is completed.

A write training operation after the read training operation iscompleted will be described below.

If the data Data used to generate the internal CRC information CRC_I islatched by the read pipe latch block 600, the second read pipe latchcontrol pulse RDCTRL2_p is generated and the data latched by the readpipe latch block 600 is outputted to the first pad PAD1, whereby thewrite training operation is completed.

If the read training result signal RDTR_r is not enabled but is in adisabled state, data is latched by the read pipe latch block 600 throughthe first pad PAD1, the write pipe latch block 300 and the firstselection block 400, and the latched data is outputted, whereby thewrite training operation is completed.

In the semiconductor memory apparatus in accordance with theembodiments, since the read training operation may be performed byreceiving data through a pad for inputting and outputting data, a largeamount of data may be latched at once, whereby a time required forperforming the read training operation may be shortened. Also, if theread training result signal RDTR_r is enabled while performing the readtraining operation, the data used in the previous read trainingoperation is latched by the read pipe latch block 600 and the latcheddata is outputted in the write training operation, without the necessityof inputting data again and latching the data by the read pipe latchblock 600, whereby a time required for performing the write trainingoperation may also be shortened.

The methods and semiconductor memory apparatuses discussed above (seeFIGS. 1-4) are particular useful in the design of memory devices,processors, and computer systems. For example, referring to FIG. 5, ablock diagram of a system employing the methods and semiconductor memoryapparatuses in accordance with the embodiments are illustrated andgenerally designated by a reference numeral 1000. The system 1000 mayinclude one or more processors or central processing units (“CPUs”)1100. The CPU 1100 may be used individually or in combination with otherCPUs. While the CPU 1100 will be referred to primarily in the singular,it will be understood by those skilled in the art that a system with anynumber of physical or logical CPUs may be implemented.

A chipset 1150 may be operably coupled to the CPU 1100. The chipset 1150is a communication pathway for signals between the CPU 1100 and othercomponents of the system 1000, which may include a memory controller1200, an input/output (“I/O”) bus 1250, and a disk drive controller1300. Depending on the configuration of the system, any one of a numberof different signals may be transmitted through the chipset 1150, andthose skilled in the art will appreciate that the routing of the signalsthroughout the system 1000 can be readily adjusted without changing theunderlying nature of the system.

As stated above, the memory controller 1200 may be operably coupled tothe chipset 1150. The memory controller 1200 may include at least onesemiconductor memory apparatus as discussed above with reference toFIGS. 1-4. Thus, the memory controller 1200 can receive a requestprovided from the CPU 1100, through the chipset 1150. In alternateembodiments, the memory controller 1200 may be integrated into thechipset 1150. The memory controller 1200 may be operably coupled to oneor more memory devices 1350. In an embodiment, the memory devices 1350may include the at least one semiconductor memory apparatus as discussedabove with relation to FIGS. 1-4, the memory devices 1350 may include aplurality of word lines and a plurality of bit lines for defining aplurality of memory cell. The memory devices 1350 may be any one of anumber of industry standard memory types, including but not limited to,single inline memory modules (“SIMMs”) and dual inline memory modules(“DIMMs”). Further, the memory devices 1350 may facilitate the saferemoval of the external data storage devices by storing bothinstructions and data.

The chipset 1150 may also be coupled to the I/O bus 1250. The I/O bus1250 may serve as a communication pathway for signals from the chipset1150 to I/O devices 1410, 1420 and 1430. The I/O devices 1410, 1420 and1430 may include a mouse 1410, a video display 1420, or a keyboard 1430.The I/O bus 1250 may employ any one of a number of communicationsprotocols to communicate with the I/O devices 1410, 1420, and 1430.Further, the I/O bus 1250 may be integrated into the chipset 1150.

The disk drive controller 1450 (i.e., internal disk drive) may also beoperably coupled to the chipset 1150. The disk drive controller 1450 mayserve as the communication pathway between the chipset 1150 and one ormore internal disk drives 1450. The internal disk drive 1450 mayfacilitate disconnection of the external data storage devices by storingboth instructions and data. The disk drive controller 1300 and theinternal disk drives 1450 may communicate with each other or with thechipset 1150 using virtually any type of communication protocol,including all of those mentioned above with regard to the I/O bus 1250.

It is important to note that the system 1000 described above in relationto FIG. 5 is merely one example of a system employing the semiconductormemory apparatus as discussed above with relation to FIGS. 1-4. Inalternate embodiments, such as cellular phones or digital cameras, thecomponents may differ from the embodiments illustrated in FIG. 5.

While various embodiments have been described above, it will beunderstood to those skilled in the art that the embodiments describedare by way of example only. Accordingly, the semiconductor memoryapparatus described herein should not be limited based on the describedembodiments.

What is claimed is:
 1. A semiconductor memory apparatus comprising: acyclic redundancy check (CRC) circuit block electrically coupled with afirst pad, and configured to generate internal CRC information from datareceived from the first pad; and a comparison unit configured to compareexternal CRC information received from outside the semiconductor memoryapparatus with the internal CRC information, and generate a readtraining result signal.
 2. The semiconductor memory apparatus accordingto claim 1, further comprising: a third pad configured for outputtingthe read training result signal and the internal CRC information,wherein the external CRC information is received through a second pad,the second pad configured for receiving an address from outside thesemiconductor memory apparatus.
 3. The semiconductor memory apparatusaccording to claim 2, further comprising: a first selection blockconfigured to electrically couple the second pad and the comparison unitor electrically couple the second pad and an address line, in responseto a training control signal; and a second selection block configured tooutput either the internal CRC information or the read training resultsignal to the third pad in response to the training control signal.
 4. Asemiconductor memory apparatus comprising: a cyclic redundancy check(CRC) circuit block configured to receive data from a first pad andgenerate internal CRC information; a training determination blockconfigured to compare the internal CRC information with external CRCinformation and generate a read training result signal, and generate acombination pulse in to response to the read training result signal anda first read pipe latch control pulse; a write pipe latch blockconfigured to receive and latch the data, and output latched data; afirst selection block configured to electrically couple an output nodeof the write pipe latch block with an input node of a read pipe latchblock in response to a training control signal; the read pipe latchblock configured to receive and latch data inputted through the inputnode thereof and output latched data to the first pad, in response to apipe input signal and a pipe output signal; and a read pipe latchcontrol block configured to generate the pipe input signal and the pipeoutput signal in response to a second read pipe latch control pulse andthe combination pulse.
 5. The semiconductor memory apparatus accordingto claim 4, wherein the training determination block comprises: acomparison unit configured to compare the internal CRC information withthe external CRC information, and generate the read training resultsignal; a pulse generation unit configured to generate a result pulse inresponse to the read training result signal; and a signal combinationunit configured to output the combination pulse when the result pulse orthe first read pipe latch control pulse is received by the signalcombination unit.
 6. The semiconductor memory apparatus according toclaim 5, wherein the pulse generation unit comprises: a delay sectionconfigured for receiving the read training result signal; is a firstinverter configured for receiving an output of the delay section; afirst logic gate configured for receiving an output of the firstinverter and the read training result signal; and a second inverterconfigured for inverting an output of the logic gate and outputting theresult pulse.
 7. The semiconductor memory apparatus according to claim6, wherein the signal combination unit comprises: a second logic gateconfigured for receiving the result pulse and the first read pipe latchcontrol pulse; and a third inverter configured for receiving the outputof the second logic gate and outputting the combination pulse.
 8. Thesemiconductor memory apparatus according to claim 4, wherein the firstselection block electrically couples the output node of the write pipelatch block with the input node of the read pipe latch block when thetraining control signal is enabled, and electrically couples the outputnode of the write pipe latch block with a write data line andelectrically couples the input node of the read pipe latch block with aread data line when the training control signal is disabled.
 9. Thesemiconductor memory apparatus according to claim 8, wherein the firstselection block comprises: a first switch configured to electricallycouple and decouple the output node of the write pipe latch block withthe input node of the read pipe latch block in response to the trainingcontrol signal; a second switch configured to electrically couple anddecouple the output node of the write pipe latch block with the writedata line in response to the training control signal; and a third switchconfigured to electrically couple and decouple the input node of theread pipe latch block with the read data line in response to thetraining control signal.
 10. The semiconductor memory apparatusaccording to claim 4, further comprising: a second selection blockconfigured to electrically couple a second pad to the trainingdetermination block and transmit the external CRC information to thetraining determination block or electrically couple the second pad to anaddress line and transmit an address to the address line, in response tothe training control signal; and a third selection block configured totransmit the internal CRC information to a third pad or transmit theread training result signal to the third pad, in response to thetraining control signal.
 11. A training method of a semiconductor memoryapparatus, comprising: a read training operation including an internalcyclic redundancy check (CRC) information generating action of receivingdata and generating internal CRC information, a comparing action ofcomparing the internal CRC information and external CRC informationinputted from an exterior and generating a read training result signal,a first outputting action of outputting the read training result signalto an exterior, and an action of inputting the data used to generate theinternal CRC information, to a read pipe latch block, and latching theinputted data, when the read training result signal is at apredetermined level; and a write training operation including a secondoutputting action of outputting the data, latched by the read pipe latchblock, outside of the semiconductor memory apparatus.
 12. The trainingmethod according to claim 9, wherein the action of inputting the dataused to generate the internal CRC information, to the read pipe latchblock, and latching the inputted data comprises: receiving the data,inputting the data to a write pipe latch block, and latching theinputted data; and inputting the data latched by the write pipe latchblock, to the read pipe latch block, and latching the inputted data, inresponse to the read training result signal.